What is the lowest quantum gate error rate ever demonstrated?

Computed from the live record dataset and the site's open model, with sources.

As of September 2026, the lowest demonstrated two-qubit gate error rate is 0.0003 (0.03%, a gate fidelity of 99.97%), set on trapped-ion hardware in July 2024. Per-platform records: Neutral Atom 0.00136, Superconducting 0.000493, Trapped-Ion 0.0003. These are measured values on real hardware, for the best qubit pair of a device, and each current platform record links to its primary source below.

Why you may have seen a lower number

Lower error rates circulate, and most of them answer a different question. This page counts one thing: the lowest two-qubit (entangling) gate error rate measured on real hardware, on the best qubit pair of a device, backed by a linked source. Numbers that look better usually relax one of those conditions, or count something narrower.

The common cases: single-qubit gate errors, which are far lower than two-qubit errors on every platform, often by orders of magnitude, but are not what limits error correction; simulated or proposed gates, where papers routinely report error rates far below anything measured, under idealised noise or with decoherence switched off; figures that count only the runs surviving postselection or erasure detection, which describe the gate conditional on no detected error (a legitimate resource for error correction, but a different number); and logical error rates of an error-corrected qubit, which are a property of a code running on many gates, not of a gate. None of those are wrong numbers, they are answers to different questions, and headlines rarely say which question was asked.

The inclusion rule cuts the other way too. A record here is the best pair, not the device: the median two-qubit error across a whole processor is typically several times higher, and the error seen in deep circuits is higher again once crosstalk and idling are included. A record is also a demonstration, not necessarily a product you can access, and sources benchmark differently (randomized benchmarking or entangled-state fidelity, with or without corrections for leakage and for state preparation and measurement), so points are comparable to within that methodological spread, not to the last digit. 2 of the 11 points in the table below are not papers but vendor disclosures (an announcement, or a live calibration value read from a public systems dashboard). Per-device details and the source URL of every point in the history are available machine-readably through the site's REST API and MCP server.

Record history: two-qubit gate error rates

Every record event in the dataset, across all tracked platforms, in chronological order. Each row lowered the record for its own platform at the time. Record error rates halve roughly every 1.5 years (neutral atom), 1.9 years (superconducting), 5.8 years (trapped-ion) on log-linear fits of these series; the fits describe the record history and are not predictions.

Trapped-Ion: Record single-pair gate error, wherever it was demonstrated (the 2016 point is a two-ion experiment). It is the laboratory frontier, not the frontier of shipped machines: whole-system trapped-ion capability on commercial processors improved about four times faster over 2020 to 2026 than this series (arXiv:2609.12146, Table VIII), because the machines were catching up to the two-ion record. Use this series for "how good can a gate be", not for "when does the machine get there".

DatePlatformTwo-qubit error rateGate fidelity
October 2012Superconducting6.53%93.47%
April 2016Trapped-Ion0.084%99.916%
July 2019Superconducting0.34%99.66%
August 2019Neutral Atom2.6%97.4%
May 2021Trapped-Ion0.06%99.94%
April 2023Neutral Atom0.5%99.5%
July 2024Trapped-Ion0.03%99.97%
July 2024Neutral Atom0.29%99.71%
September 2025Superconducting0.0519%99.9481%
March 2026Neutral Atom0.136%99.864%
September 2026Superconducting0.0493%99.9507%

How the records compare to error-correction thresholds

The two-qubit gate error rate is the single most important hardware figure of merit for fault tolerance: error correction only suppresses errors when the physical rate is below the code's threshold (1.4% for the surface code, 0.65% for the leading qLDPC code). All 3 tracked platforms are now below the surface-code threshold on record gates; the bottleneck has shifted from demonstrating sufficient fidelity to sustaining it across a full device at scale.

Being below threshold is the entry ticket, the margin is what sets the cost. Logical errors fall exponentially in the code distance only as fast as the ratio of physical error rate to threshold allows, so a platform ten times below threshold needs far fewer physical qubits per logical qubit than one twice below. The two thresholds in the table come from different noise models (a depolarizing-noise figure for the surface code, a circuit-level pseudo-threshold for the Gross code), so the two margin columns are not directly comparable to each other. Both margins are upper bounds: circuit-level surface-code thresholds are lower than the depolarizing figure (roughly 0.5% to 1%), a threshold assumes every operation in the circuit runs at that error rate, not only the best pair, and this site's own surface-code calibration reproduces measured logical error rates only with an effective error rate about twice the raw two-qubit figure.

PlatformRecord error rateSurface-code margin (upper bound)qLDPC margin (upper bound)
Neutral Atom0.136%10x below4.8x below
Superconducting0.0493%28x below13x below
Trapped-Ion0.03%47x below22x below

Compute it yourself

Every number on this page is computed from the same open model that powers the interactive evaluator and the MCP server for AI assistants.

GET https://www.quantum-expectations.com/api/fit-historic-series?seriesType=fidelity&hardwareType=Trapped-Ion

Primary sources