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Model 6.0.0: qLDPC codes, sized honestly

Published 2026-11-10 · report/model-6-0-0-qldpc

This update changes how the site treats qLDPC codes, the dense error-correction codes that promise far fewer physical qubits per logical qubit than the surface code. Qubit counts were too low, the fault-tolerant estimate could not size a qLDPC machine at all, and the gap between our error figures and published simulations was not visible. All three are fixed. Surface-code and uncorrected results are unchanged.

Qubit counts follow the published architecture

A block of either cataloged code encodes 12 logical qubits, but the architecture that makes these codes computable (arXiv:2506.03094) reserves one of them as a working qubit and joins neighbouring blocks with extra qubits. A block therefore offers 11 logical qubits for data. For the gross code that is 36.4 physical qubits per logical qubit, where we used to say 31.5, and RSA-2048 at 1399 logical qubits rises from 44,226 to 51,178 physical qubits before the factories that supply magic states.

Because the number of blocks enters the error calculation too, the error per operation rises wherever more blocks are needed than before: by about 9% for large circuits, 11% at 100 logical qubits, and it doubles at exactly 12 logical qubits, which used to fit in one block.

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Error data, side by side

Our per-operation error for these codes comes from how well a block stores information, not from simulations of operations on it, and the published simulations give different figures, usually higher. Responses for these codes now return both figures at the requested error rate, so the gap is visible as numbers rather than as a remark. The code catalog now also serves the per-operation simulation data itself, with its source and where it is assumed rather than simulated.

A full machine estimate for qLDPC codes

The fault-tolerant resource estimate, which used to size surface-code machines only, now also sizes machines built from the two cataloged codes: code blocks, factory, physical qubits, wall-clock time and the error budget, under the same two logical-error fits.

It charges every T gate as an operation across all blocks, which is the published capability model and heavier than what many real circuits need, and it leaves out terms the source does not tabulate. Its verdicts, in or out of reach, are estimates rather than bounds. For the larger code, two of the operation error rates are values the source assumes rather than simulates, and every result for that code says so.

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Source: https://arxiv.org/abs/2506.03094